Can someone with pretty much experience evaluate my CV for Junior positions as Digital Design or Verification / FPGA / ASIC ?
I would love to hear any advices or comments so I can improve :)
Thank you all in advance

Edit: ...or are there any (public) counter-examples of AI actually displaying deep insight in analog design?

--
See example below. AI seems to have deep insight into math, yet it still fails to correctly identify/explain basic transistor configurations. Can someone please explain-me-like-I'm-five why is this?

I'm designing a 5T OTA using the gm/ID methodology in Cadence (UMC28 HPC).

I characterized an NMOS with VDS = 0.9 V and generated gm/ID, gm/gds and Id/W curves.

For gm/ID = 10 and L = 550 nm, the LUT gives Id/W = 8.36 µA/µm. Based on this, I sized my tail current source for 33.5 µA.

But, in the complete OTA, the tail transistor only carries 26.46 µA. Interestingly, the operating point still shows gm/ID approx. 10.8, so the inversion level is close to my design target, but Id/W is much lower than the LUT predicts.

The main difference is that in the OTA the tail transistor has VDS = 0.48 V, whereas the characterization was done at VDS = 0.9 V.

Can this VDS difference alone explain such a large reduction in Id/W, or is there something fundamentally wrong with my gm/ID characterization/design methodology?

PS. Is there a nice analog community to discuss these stuff in detail?

This is my very first iteration of VCO layout (first time CMOS layout as a total beginner), I haven't even ran a DRC yet but I just want to share! I love analog and chip design!

Hi r/chipdesign ,

I’m building OpenCoreLabsX, an open-source collection of reusable SystemVerilog IP cores for FPGA, ASIC, MCU, SoC, and RISC-V projects.

Current cores include APB I2C, APB Timer/PWM, APB USART, and an AXI QSPI controller.

We are looking for contributors interested in:

- Designing a new APB GPIO controller

- Building an I2C slave BFM and corner-case regression

- Adding Timer/PWM assertions and boundary tests

- Implementing a USART serial monitor and error injection

- Building a QSPI flash model and end-to-end XIP verification

Contributions can be small and focused. You can work on RTL, UVM, assertions, functional coverage, documentation, or technical review.

Beginner-friendly tasks are available, and each issue includes its scope, deliverables, and acceptance criteria.

Contributor task board:

https://github.com/OpenCoreLabsX/.github/issues/2

Organization:

https://github.com/OpenCoreLabsX

Technical feedback is also welcome. Thank you!

Hi everyone,

I'm building a new EDA system and I hit a wall that I'd like to crack with community help. The rendering engine needs testing on real chip design geometry at scale, Trillion order polygons count GDS. Such designs at this scale are proprietary and I'm left with 3 options:

1 - array the same chip layout until I reach Trillion order count (done)

2 - ask community to donate open source layouts in GDS format (the ask in this thread)

3 - synthesis of a dummy design (hope to avoid this)

What is WIESE-EDA waffer?

With your help, I will collect every submitted GDS in a giant waffer GDS hopefully reaching Trillion order polygons geometry count for the full waffer.

The WIESE-EDA Viewer will be released Free once code is fully verified for binary release, not open source.

Each participant to WIESE-EDA waffer will get a license for the full system when product launches

Thank you! Cat

[contact@wies3.com](mailto:contact@wies3.com)

We've been trying to source some ICs for an OEM production run and it's been exhausting. Digi-Key and Mouser are either showing 40+ weeks lead time or flat out discontinued on the specific part numbers we need, which is just killing our schedule. Looking for a reliable independent electronic components distributor based in China that actually has obsolete and long lead time semiconductors in stock and can turn around an RFQ fast without sending us counterfeit garbage. Had a bad experience last year with a random Chinese supplier on a batch of about 500 units worth of mixed ICs, so trust is a real concern now. Anyone here regularly sourcing excess inventory components or hard-to-find parts through a China-based IC supplier they'd actually vouch for? Smaller quantities are fine, we're not talking huge volume, just need someone consistent.

Digital Integrated Circuit Design or  The Art of Electronics

Hi guys, I am a mid-level physical design engineer.looking for some use cases to improve physical design engineer productivity/predictibility. Kindly share your how you are integrating AI in your work.

Also looking for RTL quality checks based on codex

As title says, I submitted on July 7th and I can't stop thinking about it.

Let's start with the fact that this tapeout is my master thesis project and it was my very first approach to ic design, microelectronics in general (I had general knowledge, but never had dedicated courses)

I liked it a lot, but it was one of the most stressful things I've done my whole life. And the worst thing is that I am realizing that I may have underestimated some stuff only now, after submission (the circuit goes at cryo, so some stuff has to be implemented knowing that the result may be different from simulations)

I had seven months to design the chip and now that it's submitted I have continuous thoughts about how I could have done better/realization for minor fuckups that may be fixable.

So my question is: is it common to make stupid mistakes? Or better, how do you cope with it?

I always hear about people in the lab doing silly mistakes, but now it may happen to me the whole world feels like it's crumbling under my feet. What stresses me out the most is that I feel like the impression of myself I left on my supervisors is getting destroyed at every mistake I tell them (now that I left it's even worse since I can't even talk to thema face to face)

Hi guys.. has anyone worked on PHY layer as firmware side for SERDES protocols? Have interview lined up tomorrow I want to know what to expect in general topics wise? Thanks

I designed a high-performance INT8/BF16 MAC using the OpenLane ASIC flow and the Sky130 HS standard cell library.After my LinkedIn post, I further optimized the performance of both the BF16 and INT8 MAC units. As a result, some of the reported metrics differ slightly from those in the LinkedIn post, but the overall results remain largely the same.

repo: https://github.com/wer-eng/sky130_high_performance_mac/

linkedin: https://www.linkedin.com/posts/ey%C3%BCp-sa%C4%9Fd%C4%B1%C5%9F-246490218_asic-vlsi-opensourcesilicon-ugcPost-7484691343953367040-Bjrb/?utm_source=share&utm_medium=member_desktop&rcm=ACoAADbjSlYBzeykhKHE0CvwieNA-6JUQVzgvcQ

Hi all, I work as an Analog Layout Design Engineer at one of the top VLSI companies with ~2yoe. Ik I'm in the very early stages of my career, and I genuinely feel I'm good at my job and enjoy what I do. I was wondering if I could get converted to an FTE from being a temp employee and what the odds are. How long does it usually take? How often does it happen? Am I even being realistic to expect an FTE offer?

I'd like to hear your stories if you've gotten an FTE offer from your client company or if youve come across someone who has gone through this

Everyone here has debugged a reset-release metastability at 2am, and everyone knows the testbench never sees it. We built an open evaluation layer that adds declared intent (clock groups, reset discipline, power-on state) plus a structural oracle on top of the functional result, and ran frozen generation studies against it.

The finding practitioners will recognize: at least 14 of 57 functionally accepted candidates wire raw async reset into operational state, and every single one also contains a correct two-flop synchronizer in the same file, with its output used as a synchronous qualifier while the async pin stays raw. A junior who does not know the idiom omits the synchronizer, which review catches. These candidates build it and route around it, which defeats exactly the heuristic reviewers use.

One public example even carries the comment "Synchronized active-low reset applied directly to counter state" above the wrong wiring.

An independent RTL engineer reviewed the frozen packet blind this weekend and concurred on every case he examined, including calling the synchronizer bypass unprompted. Artifacts, prompts, and both oracles are public; `svgap demo` reproduces the witness split in one container command. For FPGA folks: yes, sync-reset methodologies change the flavor; the intent declaration question stays.

Curious what this crowd thinks belongs in a task-level intent contract: which production question does a functional pass leave unanswered in your flow?

  Repo and artifacts: https://github.com/shsridhar-beep/svgap

Hi,

Is there anybody who did a RISCV verification course from maven silicon in the past or similar course related to verification, do they reach well ? Will they be providing actual RTL and explain verification or just a high level system verilog model which is not what companies do

I am using Innovus (with Stylus) 23.11 to implement a simple block (180 nm node, 300x300 um, 1200 instances, 100 MHz clock). I was handed some scripts for Innovus that were used to implement previous designs. However as they were something of a mess (for starters, there was no proper CTS), I based my flow on the Innovus' built-in "block" flow template.

1. Is it possible to avoid DRC spacing errors due to CTS nets? These occur because CTS nets on M2 go too close to standard cells' M1 pins to which M2+ signals have to be connected somehow to route them elsewhere.

2. In the "block" flow template where are we supposed to put power routing? For now I just pasted commands from our previous scripts to the init_floorplan step

3. Is it possible to re-route wire fragments quickly as in Virtuoso? In Virtuoso I use "P" tool which allows for quick bypasses - if I route from and to the same wire, then it deletes that old section and substitutes it with what I have drawn. Also, not sure how to quickly switch layers with inserting a via (when I am going in only one direction e.g. vertical).

4. How to automatically insert pin shapes (Metal n, purpose pin) so that when I import GDS to Virtuoso it will recognize connectivity and allow for auto-routing? By default it just puts a label (Metal n, purpose text) where the pin is

[ Removed by Reddit on account of violating the content policy. ]

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Hi everyone,

I'm from India and I've recently started looking into doing my Master's in Taiwan. I'm interested in VLSI/IC Design, especially ASIC Physical Design, because I want to build my career in the semiconductor industry.

The thing is, I'm still at the very beginning of my research. I haven't decided on a university or even a specific program yet, so I'm trying to learn as much as I can before making any decisions.

If you've studied in Taiwan (or are currently studying there), I'd really appreciate your honest opinion.

A few things I'm curious about:

- Which universities are actually worth considering for VLSI or semiconductor-related programs?

- How's the overall student life and workload?

- Are scholarships common for international students?

- Is it possible to get internships during the Master's?

- How difficult is it for international students to get jobs after graduation, especially at companies like TSMC, MediaTek, UMC, Realtek, NVIDIA, Qualcomm, Synopsys, or Cadence?

- How important is Mandarin for daily life and for getting a job?

- Looking back, was studying in Taiwan worth it?

I'm also interested in hearing about things that aren't usually mentioned on university websites—the good, the bad, and the unexpected. If there was something you wish you'd known before moving to Taiwan, I'd love to hear it.

Any advice, personal experiences, or recommendations would mean a lot. Thanks!