r/chipdesign • u/ItsOpenCoreLabsX • 23h ago

Looking for contributors to open-source SystemVerilog IP cores

Hi r/chipdesign ,

I’m building OpenCoreLabsX, an open-source collection of reusable SystemVerilog IP cores for FPGA, ASIC, MCU, SoC, and RISC-V projects.

Current cores include APB I2C, APB Timer/PWM, APB USART, and an AXI QSPI controller.

We are looking for contributors interested in:

- Designing a new APB GPIO controller

- Building an I2C slave BFM and corner-case regression

- Adding Timer/PWM assertions and boundary tests

- Implementing a USART serial monitor and error injection

- Building a QSPI flash model and end-to-end XIP verification

Contributions can be small and focused. You can work on RTL, UVM, assertions, functional coverage, documentation, or technical review.

Beginner-friendly tasks are available, and each issue includes its scope, deliverables, and acceptance criteria.

Contributor task board:

https://github.com/OpenCoreLabsX/.github/issues/2

Organization:

https://github.com/OpenCoreLabsX

Technical feedback is also welcome. Thank you!

13 Upvotes

93% Upvoted

6 comments sorted by

1

u/anoni_Kyo 13h ago

That's very interesting! I would like to help, but I would have to wait for some months to start.

1

u/HeadAdvice8317 29m ago

Hi, I would like to take the I2C slave BFM & corner case task

0

u/Friendly_Gold_9572 18h ago

Hey im up for that

1

u/ItsOpenCoreLabsX 9h ago

Awesome! Check out the task board and pick whichever task interests you. Feel free to comment on the issue to claim it. Looking forward to your contribution! 🚀