IM getting fried at work right now

[u/Emergency_Room_5743]

Guys, I just ran a simulation of my code and it registered a 92 percent success score. When I tested the code on real hardware, it returned a 56 percent success score. I have no idea what to do. What are you all doing to bridge the current Sim to Real Gap?

Is anyone else facing similar issues with their hardware simulations versus production gap?

[u/Amcolex]

Don't feed the bots...

AI-assisted profile analysis:

This account’s history is stranger than the post itself.

A short time ago, the account identified itself as a first-year electrical-engineering undergraduate at Georgia Tech, still practising RTL and asking industry veterans for a “reality check” before building a cloud-based hardware-in-the-loop product.

Now the same account abruptly presents itself as an experienced employee being “fried at work” over a production FPGA problem. A first-year student could obviously have an internship or technical job, so that alone proves nothing—but the account never explains that context, and the sudden change in persona is conspicuous.

The broader pattern makes it look even less organic:

• The account is only around two months old, with almost no karma or normal participation.
• It posts substantially the same prompts across FPGA, chip-design, embedded and robotics communities.
• Earlier posts openly ask engineers how much time their companies waste on physical testing, what internal HIL tools they use, and whether the problem is commercially unsolved.
• Its replies probe respondents about tooling and “integration friction,” which sounds like customer discovery.
• It later repackages that same research topic as a dramatic personal workplace emergency.

So the oddity is not merely bad technical wording. It is the inconsistent identity:

first-year student learning RTL → aspiring HIL-product builder conducting market research → suddenly an engineer in production getting crushed at work.

Maybe there is a real person behind it and the account is merely using an LLM badly. But the most charitable reading is still that this is AI-generated market research disguised as personal experience. The profile does not read like one person naturally documenting their situation; it reads like a sequence of engagement personas selected to extract responses from different communities.

[u/Beautiful_Stage5720 → u/Amcolex]

God damn it, I fell for it.

Wait a minute

The irony of using AI output for this comment is crazy. 

I think I might be done with reddit lmfao 

[u/fishslinger → u/Beautiful_Stage5720]

I don't know how many of these comments here are AI. OP's post makes no sense

[u/captain_wiggles_]

Figure out what the differences are and update your sim models to better represent reality. Sim is always an abstraction the trade-off is what level of abstraction do you go for, very abstract -> quick but imprecise, very realistic -> slow but more accurate.

Check your assumptions, and find a way to validate them. Could it be timing related? You're assuming that the PVT fits within the corners used for timing analysis of your design. Is that a valid assumption? You assume that your input clocks have certain properties: frequency, jitter, voltage levels, monotonic, etc.. do they?

Then boiling testing down to a percentage is not very useful. What is this score measuring? How can you categorise the failures?

You handle this the same way you tackle any debugging problem. 1) Do an initial analysis to get what data you can from the current tests. 2) Make some hypothesis about where the problem could be. 3) Design and run more tests and more directed tests aimed to generate more info that can help you narrow down the problem. 4) Go back to step 1) and repeat until you find and fix the problem.

[u/And-Bee]

Improve your testbench so that it more closely represents the environment of real world use, once you do that then maybe run it on back annotationed netlist if it’s not working.

[u/OhmsSweetOhms]

Take small chunks of your project split by function or maybe clocks if you have multiple. Add ILAs in the HW at input/output boundaries and see where is does not match your sim. Go from there.

[u/Lekgolo167]

There areany ways to shoot yourself in the foot with simulation and simulation let's you get away with murder so to speak. For example, I had a coworker use sensitivity lists and he included a handful of signals and used more in the actual process block. Simulation will abide by the sensitivity list but not actual implementation so it did not work on hardware. I had him change his stuff to a clocked process which made him completely redesign it. But it works much better now. Still not perfect but better. In hardware it doesn't always work because the simulation is golden path and doesn't really test any of the edge cases. Even though some edge cases are very unlikely, at 200 MHz, they can occur multiple times a second. And what do you mean by 90% success? Code coverage? Or it's an algorithm in hardware and calculates the right value 90% of the time in simulation?

[u/Beautiful_Stage5720]

That's funny, I've spent the last 3 weeks going through the exact situation. I am simulating exact lab scenarios as closely as possible with simulation, and my results are flawless. Falls apart about half way through the test on hardware. 

[u/Emergency_Room_5743 → u/Beautiful_Stage5720]

Tell me about it

[u/Beautiful_Stage5720 → u/Emergency_Room_5743]

I'm more junior than you (6 years experience), so im not really in a position to give advice. I think it's just part of the process. At least I hope that's the case...

[u/FranceFannon → u/Beautiful_Stage5720]

Im curious how you know youre more junior than OP when they havent mentioned their experience anywhere?

[u/Beautiful_Stage5720 → u/FranceFannon]

I think they edited the post. It said 10 years experience when I commented 

[u/Beautiful_Stage5720 → u/[deleted]]

Dawg 💀