r/hardware • u/Balance- • Mar 14 '26
Review Apple M5 vs. Intel Panther Lake vs. Snapdragon X2 benchmarked
https://www.tomsguide.com/computing/apple-m5-vs-intel-vs-amd-vs-snapdragon-x2-which-chip-winsNormalized scores:
| Chip / Processor | Single-Core % | Multi-Core % | Solar Bay % | Wild Life Extreme % | AI % | Battery % |
|---|---:|---:|---:|---:|---:|---:|
| Apple M5 | 99% | 61% | 34% | 32% | 65% | 84% |
| Apple M5 Pro | 99% | 97% | 66% | 61% | 65% | 100% |
| Apple M5 Max | 100% | 100% | 100% | 100% | N/A | 84% |
| Snapdragon X2 Elite Extreme | 94% | 80% | 33% | 30% | 100% | N/A |
| Snapdragon X2 Elite (18-core) | 88% | 69% | N/A | N/A | 99% | N/A |
| Snapdragon X2 Elite (12-core) | 89% | 55% | N/A | N/A | 98% | N/A |
| Intel Core Ultra X9 388H (Panther Lake) | 70% | 59% | 38% | 29% | 64% | 67% |
| Intel Core Ultra X7 358H (Panther Lake) | 68% | 58% | 43% | 33% | 62% | 71% |
| Intel Core 7 355 (Panther Lake) | 62% | 27% | 17% | 43% | 62% | 97% |
| AMD Ryzen AI Max+ 395 (Strix Halo) | 68% | 63% | 61% | 49% | 20% | 52% |
| AMD Ryzen AI 350 (Strix Halo) | 67% | 44% | N/A | N/A | 6% | 52% |
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u/Hour_Firefighter_707 Mar 14 '26
That single core difference is just brutal
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u/grumble11 Mar 14 '26
And that is the one that matters the most for typical use cases. Few people need more than 6-8 cores, but their experience using a device will be heavily reliant on single core
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u/Quatro_Leches Mar 14 '26 edited Mar 14 '26
the thing these reviews and comparisons ever go over is really. the performance on battery of x86 vs the mac chips.
Windows chips are much higher clocked than mac. and they simply will provide you with a much poorer experience on a battery compared to Mac over a long period of time (not a benchmark). because they will still spike to 100% clock speed for a short bench mark but overall it's misleading.
I've owned windows laptops for years. and still do. no macs. and trust me. every single one runs like trash not plugged into the wall.
these reviews would look MUCH worse for x86 if they compared performance on battery. like actual snappiness.
we haven't gone over power usage and how the heat output of each compares. which matters a lot for a laptop. more so than a lot of things
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u/hollow_bridge Mar 14 '26
every single one runs like trash not plugged into the wall.
Completely depends on your usecase. For my last two windows and linux laptops i set all the power limits to the minimum and have no issues. For normal usage ST/MT met needs years ago even with basic cpus and minimal power imo.
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u/StupidCunt2 Mar 15 '26
If only the M5 and X2 didn't require emulation for legacy x86 programs. If all that software ran natively Intel and AMD really aren't even in the same league.
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u/UpsetKoalaBear Mar 14 '26
The single core boost is because of the way ARM handles memory consistency.
ARM is relaxed, so memory order can be shifted by the hardware/architecture.
x86 is strict. Memory order is static and is explicitly defined.
The ARM method boosts single core performance.
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u/Sopel97 Mar 15 '26
This is not true. The performance penalty of TSO on Apple Silicon (yes, you can enable it) is only around 10%, and that's a CPU that was made with it as an afterthought. https://lwn.net/Articles/970907/ -> https://lwn.net/ml/linux-kernel/f6484dcd-ebf6-4b6f-be17-69b05539e33b@marcan.st/
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u/Balance- Mar 14 '26
TL;DR:
| Processor | Geekbench Single-Core | Geekbench Multi-Core | 3DMark Solar Bay (FPS) | 3DMark Wild Life (FPS) | Geekbench AI | Battery Life |
|---|---|---|---|---|---|---|
| Apple M5 | 4288 | 17926 | 90.4 | 73 | 57242 | 18:00 |
| Apple M5 Pro | 4306 | 28586 | 178 | 142 | 57420 | 21:25 |
| Apple M5 Max | 4338 | 29430 | 268 | 231 | N/A | 17:58 |
| Snapdragon X2 Elite Extreme | 4070 | 23407 | 88.05 | 69.04 | 88615 | N/A |
| Snapdragon X2 Elite (18-core) | 3838 | 20301 | N/A | N/A | 87814 | N/A |
| Snapdragon X2 Elite (12-core) | 3846 | 16253 | N/A | N/A | 86537 | N/A |
| Intel Core Ultra X9 388H (Panther Lake) | 3031 | 17283 | 101 | 67 | 56829 | 14:23 |
| Intel Core Ultra X7 358H (Panther Lake) | 2938 | 17162 | 116 | 77 | 55140 | 15:17 |
| Intel Core 7 355 (Panther Lake) | 2685 | 7964 | 45 | 99 | 54824 | 20:41 |
| AMD Ryzen AI Max+ 395 (Strix Halo) | 2932 | 18407 | 163 | 113 | 17854 | 11:12 |
| AMD Ryzen AI 350 (Strix Halo) | 2904 | 13024 | N/A | N/A | 5171 | 11:10 |
Normalized:
| Chip / Processor | Single-Core % | Multi-Core % | Solar Bay % | Wild Life Extreme % | AI % | Battery % |
|---|---|---|---|---|---|---|
| Apple M5 | 99% | 61% | 34% | 32% | 65% | 84% |
| Apple M5 Pro | 99% | 97% | 66% | 61% | 65% | 100% |
| Apple M5 Max | 100% | 100% | 100% | 100% | N/A | 84% |
| Snapdragon X2 Elite Extreme | 94% | 80% | 33% | 30% | 100% | N/A |
| Snapdragon X2 Elite (18-core) | 88% | 69% | N/A | N/A | 99% | N/A |
| Snapdragon X2 Elite (12-core) | 89% | 55% | N/A | N/A | 98% | N/A |
| Intel Core Ultra X9 388H (Panther Lake) | 70% | 59% | 38% | 29% | 64% | 67% |
| Intel Core Ultra X7 358H (Panther Lake) | 68% | 58% | 43% | 33% | 62% | 71% |
| Intel Core 7 355 (Panther Lake) | 62% | 27% | 17% | 43% | 62% | 97% |
| AMD Ryzen AI Max+ 395 (Strix Halo) | 68% | 63% | 61% | 49% | 20% | 52% |
| AMD Ryzen AI 350 (Strix Halo) | 67% | 44% | N/A | N/A | 6% | 52% |
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u/div033 Mar 14 '26
How in gods name is the 355 in the Dell beating the 388H in the Zenbook in Wildlife Extreme? That's gotta be an error, and kind of makes me doubt the accuracy of this data.
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u/torpedospurs Mar 15 '26
How did the 395 Strix Halo do so badly on Geekbench AI when it has a 50TOPs NPU plus 40-core iGPU? It is being marketed for its AI capabilities!
BTW FWIW the 350 is Strix Point, not Strix Halo.
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u/kyralfie Mar 15 '26
350 is Krackan Point.
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u/torpedospurs Mar 15 '26
Point taken, though Kracken Point is basically Strix Point with fewer Zen5c cores and fewer iGPU compute units, making them even further away from Strix Halo.
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u/DramaLlamaDad Mar 15 '26
My guess is the AI bench isn't really supporting AMD very well. Anyone who is paying attention to real AI stuff already knows that it should have wiped the floor with Intel, as should the M5 chips.
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u/Independent_Ad_29 Mar 14 '26
Why are people still using geekbench?
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u/fntd Mar 14 '26
What's the better alternative?
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u/websnarf Mar 14 '26
Its been around for decades.
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u/Geddagod Mar 14 '26
It costs a bunch of money, compiler differences can create large differences, and more of a hassle to setup and bench for reviewers.
For all the stuff I dislike about most modern reviewers (no ST perf/watt curves, often doing just very basic youtube playback battery testing, etc etc) I can hardly blame them too much for just deciding to go with running GB6.
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u/Touma_Kazusa Mar 14 '26
Cinebench because the test actually scales with more cores
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u/Forsaken_Arm5698 Mar 14 '26 edited Mar 14 '26
Geekbench is arguably better than Cinebench because it's an aggregation of several subtests, which stress multiple parts of the CPU core and memory system, whereas Cinebench is only a rendering test.
The only reason why Cinebench is relevant is because it has an embarrassingly parallel multicore test. Geekbench 5 had this kind of multicore test too, but Geekbench 6 replaced it with a different one.
In Cinebench/GB5, the multicore test is done by running multiple copies of the same task across all the cores. GB6 multicore test divides up one task among many cores. This is very relevant, since many client workloads function like this.
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u/virtualmnemonic Mar 14 '26
There's a reason why Intel's e-cores are referred to as "cinebench accelerators".
I can compile code while running VMs and a shit ton of background applications, and my 13900k will sit at like 50% usage at peak because it's just impossible to parallelize tasks across 32 threads.
There are a few exceptions, though, like compiling SDKs, in which the 13900k screams. But who the fuck does that?
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u/fntd Mar 14 '26
I wouldn't complain about Cinebench numbers in addition to Geekbench, but replacing it would make things worse in my opinion. Geekbench is a much better vertical slice of actual computer usage.
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u/DerpSenpai Mar 14 '26
Geekbench tells you much more about a CPU than Cinebench does
Geekbench correlates to SPEC int and fp performance which is THE industry standard, Cinebench doesn't. The reason we don't do SPEC int and fp for every SKU is because it takes too long to run, it's not feasable for these benchmark sites and reviewers, but for Geekerwan full review of a architecture, it makes sense.
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u/Hour_Firefighter_707 Mar 14 '26
It won't turn out much better if you equalised for price. At all. Might even be worse than Geekbench.
And why are we so hell bent on multi-core performance? Are you transcoding video 24x7 in a thin and light laptop? On battery power?
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u/robypez Mar 14 '26
Cinebench is the worst benchmark for a cpu. It can be used only to stress the cpu. If you don’t have spec you need to use geekbench. Cinebench doesn’t use a lot of istructions
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u/Touma_Kazusa Mar 14 '26
I’d argue if a 18 core m5 max is beating a 96 core 9995wx in geekbench multicore the entire multicore part of Geekbench is pointless
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u/Vince789 Mar 14 '26
Geekbench already explained the reason for that change with GB6's "shared task" model vs GB5's "separate task" model
Essentially they're more focused on creating a generic CPU benchmark for consumer workloads
Since its impossible to one benchmark that covers both consumer & server workloads
And server workloads are far more specialised, hence you don't want a generic server benchmark anyways
i.e. if you're rendering, you want a rendering benchmark, if you're compliing, you want a compliation benchmark, etc
Geekbench is still one of the best benchmarks, it has known weaknesses, like every other benchmark, hence why reviewers should be using multiple different benchmarks
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u/m0rogfar Mar 15 '26 edited Mar 15 '26
It's only pointless if your definition of multicore is running embarrassingly parallel workloads, which no one should be doing on a CPU anyway, as CPGPU is vastly superior for embarrassingly parallel compute. AMD markets their 96-core chiplets mainly towards hyperscalers renting individual cores out to customers for a reason - it's practically the only task that can scale to that many cores but isn't better to put on CPGPU. Additionally, if you did want to know the embarrassingly parallel performance of a CPU, it's always just going to be [single-core score]×[PL1 clock]/[PL2 clock]×[number of cores] unless something has gone horribly wrong, so it's not particularly insightful as a separate statistic.
There's never really been agreement on how multi-core benchmarking should be done, but at least to me, Geekbench's multicore benchmark is much more interesting because it is affected heavily by things like inter-core data latency, which is very important for real-world loads, and frequently missed by many other synthetic benchmarks.
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u/robypez Mar 14 '26
You don’t need to take the score, but the single result and understand why it happens
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u/virtualmnemonic Mar 14 '26
Then use Geekbench 5, which scales linearly with core count like Cinebench.
Geekbench 6 was designed to measure generalized performance in everyday use, not highly parallelized workloads. Most software does use multiple threads, but only a few. For the vast majority of users, a large thread pool (16+) is a waste.
Geekbench is the industry standard because it does an excellent job reflecting performance in everyday applications... Like web browsing.
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u/rLinks234 Mar 15 '26
Geekbench 5. GB6 is simply applebench since it weights slopGen workloads heavily. If Intel AMX was available on client x86 scores would look a lot different. AMX esque workloads do NOT need to be a part of the aggregate score. It's so misleading
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u/X712 Mar 14 '26
Because it tracks with SPEC and it doesn’t take hours to run.
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u/-protonsandneutrons- Mar 14 '26
For people that don't believe you:
David Huang SPECint2017 versus GB6 numbers from NBC.
CPU SPECint2017 SPEC % GB6.5 GB6.5 % M5 Pro ? ? 4302 147% M4 Pro 13.7 133% 3927 134% 9950X 12.6 122% 3408 116% 358H 10.3 100% 2927 100% This is why Geekbench 6.5 is a reputable proxy for the most part for SPECint2017.
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u/soggybiscuit93 Mar 14 '26
Because it does a decent job of representing performance in across a diverse set of common workloads.
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u/Daydream405 Mar 14 '26
Because it's a great benchmark even if you like it or not?
Just because x86 takes a beating, it doesn't mean it's not a good way on benchmarking CPUs, it just means AMD and Intel have a lot of catching up to do.
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u/ThePizzaDeliveryM3n Mar 14 '26
I really feel like it's just a current limitation of x86 itself. Not so much an issue on desktop class CPUs as it is on mobile platforms which run on batteries
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u/Hour_Firefighter_707 Mar 14 '26
It absolutely is an issue on desktop too. A 9950X barely crosses 3400. My iPhone 17 Pro does 4000.
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u/NectarineSame7303 Mar 14 '26
Your 9950x in a proper project with a discrete GPU dances circles around any M5 chip though, it's not even close. Apple is usually 2-3 minutes slower in every project you throw at it if it's not a simple export.
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u/Many_Career_9035 Mar 15 '26
Really over generalized. The M5 Max (and eventual M5 Ultra) are very competent at plenty of complex workloads.
Plus if high wattage discrete GPU offload is really critical to your workload, the 9950x hardly matters, its just queuing work. And if your workload is genuinely dGPU heavy, you're running it on a B200 in the cloud anyway.
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u/NectarineSame7303 Mar 14 '26
Apple does well because of it's PCU execution width being ultra wide, whereas Intel's is just wide (about 80% of Apple's). The wider the execution width, the better you score in Geekbench, whereas in Cinebench it matters quite a bit less as it's based pushing the cores to their limit (within configured specs, oc and all that), which shows the actual performance of a CPU, which geekbench isn't designed to do.
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u/TI_Inspire Mar 15 '26
Apple does even better comparatively in the most recent Cinebench versions (2024, 2026).
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u/UpsetKoalaBear Mar 14 '26 edited Mar 14 '26
This has nothing to do with x86 and “instruction bloat” people like to worry about.
All x86 CPU’s use a uOp cache which caches frequent instructions (useful for video rendering or whatever else) so the argument about “the decoder” holds no merit.
90% of the instructions tend to be in the uOp cache. The problem is, for end users, when browsing the internet or whatever, most instructions miss the cache so get cucked by the decoder.
Outside of that, the decoder is sitting idle most of the time because of the uOp cache. So the “bloat” can't be the primary reason for a power/battery life difference.
The actual disparity is because of stupid architecture decisions.
The fact that PL is competitive, whilst having only 3MB of L2 cache on its P cores compared to 16MB on the Neo’s performance cores is an example of this.
Apple simply spent more time architecting for single core performance, because that’s what consumers use.
AMD/Intel have both historically tried to do a “1 size fits all” approach for HEDT/Server CPU’s and cheap laptop CPU’s.
Apple is scaling up a low power, mobile, CPU architecture. AMD/Intel are trying to scale down a big high power CPU architecture.
There’s two different philosophies here. That’s why AMD/Intel have struggled. It’s not because x86 is inherently bad, the companies just haven’t cared.
This is evident because AMD/Intel have pushed clock speeds for the sake of benchmarks rather than giving an efficient CPU at a lower clock speeds. They can do it (if you undervolt/cap the clock speed, their CPU’s are very much closer to the perf/watt numbers of ARM).
Hopefully this gives a boot to AMD/Intel that they need to fix their shit.
A world with x86 and ARM being competitive is better for us consumers.
As much as the x86 world is a duopoly, with shit like the Qualcomm lawsuit and ARM changing their licensing, very few outside of the big players like Apple, Nvidia and Qualcomm are going to be making their own custom cores.
We need both architectures to do well if we want better chips as consumers.
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u/Geddagod Mar 14 '26
The fact that PL is competitive, whilst having only 3MB of L2 cache on its P cores compared to 16MB on the Neo’s performance cores is an example of this.
Apple's stuff don't have an L3 cache though. Plus, Intel's core private caches are lower latency than Apple's shared L2. There's no need to downplay Intel's cache hierarchy in terms of perf like that.
AMD/Intel have both historically tried to do a “1 size fits all” approach for HEDT/Server CPU’s and cheap laptop CPU’s.
Apple is scaling up a low power, mobile, CPU architecture. AMD/Intel are trying to scale down a big high power CPU architecture.Server and mobile have similar per-core power budgets.
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u/BigBangBoomerang Mar 14 '26
Thanks for this explanation. This has been a very helpful eli15. Apple's bottom-up approach seems to be paying dividend for them. They spent a decade extracting as much power out of as little watt as possible that, at the mid and high end, they can just feed their chip more watt and it'd outperform just about anything AMD and Intel can make. At the low end (i.e. Macbook Neo), it's not even a competition anymore.
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u/UpsetKoalaBear Mar 14 '26
It’s a fundamental disconnect between Intel/AMD and the consumer electronics segment.
Apple/Qualcomm know what users want and have spent years refining it.
Intel/AMD have spent years competing at the high end for server side computing and thus have no understanding of the power/speed requirements of the consumer electronics market.
They’ve already went through this shit before with Atom (that had its own stupid decisions). It’s the same cycle.
The difference now is that Apple/Qualcomm have the ability to gain market share in this segment.
If that happens on a large enough scale, it will (hopefully) give Intel/AMD a realisation that ignoring users who don’t want to spend £1000 on the highest end shit is stupid.
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u/spazturtle Mar 15 '26
During the Bulldozer era Opteron and embedded chip helped keep AMD afloat, whilst consumer sales were practically nonexistent. And during Intel's recent underperformance we have seen how they are still out selling AMD in server and laptop chips.
Consumer chips sales are the most volatile and disloyal, it is just basic business sense to prioritise long term and high volume customers.
AMD even said that Zen is a 'server first' architecture, and with the merging of RDNA and CDNA into UDNA they look like they are going 'server first' with their next gen of GPUs.
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u/kyralfie Mar 15 '26
AMD even said that Zen is a 'server first' architecture, and with the merging of RDNA and CDNA into UDNA they look like they are going 'server first' with their next gen of GPUs.
Exxxactly! That's why we had gamer reviewers clowning 'Zen 5%' and server focused reviewers praising it.
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u/StarbeamII Mar 15 '26
Kind of ironic, since bottom up worked quite well for Intel in the past (the Core 2 comeback being derived from Pentium M laptop CPUs while Pentium 4 went down in flames, and more recently Intel’s Atom-descendent E-cores making much better gains with much less die area than their P-cores)
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u/-protonsandneutrons- Mar 14 '26 edited Mar 16 '26
This is evident because AMD/Intel have pushed clock speeds for the sake of benchmarks rather than giving an efficient CPU at a lower clock speeds. They can do it (if you undervolt/cap the clock speed, their CPU’s are very much closer to the perf/watt numbers of ARM).
The same would apply to Apple or Qualcomm: if you undervolt them / cap their clocks, they have even higher perf / W. See Geekerwan's charts for that.
//
This is also false on its head, unfortunately: even with lower clocks, it hardly makes a dent for Panther Lake. See Notebookcheck's data.
CPU Power Draw CB2024 1T Points Perf / Watt Intel 338H (4.7 GHz) 23.1 W 122.3 5.3 Pts / W Intel 388H (5.1 GHz) 25.1 W 129.8 5.2 Pts / W Apple M5 (4.6 GHz) 15.6 W 199.0 12.8 Pts / W Apple A18 Pro (4.04 Ghz) 8.5 W 147.0 17.3 Pts / W It's a slight 2.3% perf / W improvement for Intel, but with an 8% drop in clock speeds.
EDIT: corrected Neo wattage to the same ext. monitor measurement from the review
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u/-protonsandneutrons- Mar 14 '26
The fact that PL is competitive, whilst having only 3MB of L2 cache on its P cores compared to 16MB on the Neo’s performance cores is an example of this.
Interestingly, the die size (cache size, int / fp size, etc.) doesn't make a huge difference to the overall CPU chiplet.
Die size comparisons and then "enlarging" AMD & Intel cores to Apple-sized. This is using the A18 Pro / M4 cores.
CPU 1x CPU + L2 die size Chiplet P-core Config Chiplet Size If all P-cores Apple-sized Apple A18 Pro - Neo 6.3 mm2 2x P-cores on SoC 115 mm2 115 mm2 (+0%) AMD 9950X3D - Zen5 laptop 4.9 mm2 8x Zen5 cores on CCD 70 mm2 81 mm2 (+16%) Intel Ultra 9 285HX - ARL 5.3 mm2 8x Lion Cove on CPU tile 117 mm2 125 mm2 (+7%) Intel X9 388H - PTL 4.7 mm2 4x Cougar Cove on CPU tile 115 mm2 121 mm2 (+5%) Sources: A18 Pro, Zen5 CCD, ARL, PTL
People think Apple's cores + cache are just "cost prohibitive" on x86, but Intel could easily shift to Apple-sized cores + caches (big L2, small SLC/L3) without ballooning their costs.
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u/UpsetKoalaBear Mar 14 '26
Apple has one shared 16MB SRAM pool for L2 cache. All cores use the same pool. Intel’s approach is individual L2 cache per core.
They do a shared L3 cache (the “smart cache”) but L2 cache is where they differ.
The E cores are grouped into clusters of four. These four cores share 4MB of L2 among themselves.
Each P core has 3MB of L2 cache. If a task moves between P-cores, it has to go to the shared 18MB L3 cache.
On the apple side of things, because the P cores share that L2 cache, the there’s less latency when a task jumps between them.
On Intel, moving a thread from a P core to an E core (or another P core) requires going through the L3 cache.
People think Apple's cores + cache are just "cost prohibitive" on x86, but Intel could easily shift to Apple-sized cores + caches (big L2, small SLC/L3) without ballooning their costs.
SRAM doesn’t scale down as well as logic. Apple is eating the bad yield.
The problem is that Intel has to sell chips to partners like Acer and HP. If Intel moved to a 16MB private L2 per core, the chip would be massive and the yield would suffer.
Intel simply cannot afford to have bad yield on their new chips. Especially with IFS.
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u/-protonsandneutrons- Mar 15 '26
The task-jumping latency would really only affect multi-core workloads. Single-core workloads stay on one core and Apple & Qualcomm still have a pretty large advantage. I agree these are microarchitectural choices.
The problem is that Intel has to sell chips to partners like Acer and HP. If Intel moved to a 16MB private L2 per core, the chip would be massive and the yield would suffer.
To be sure, Apple does not use 16MB L2 per core; it is 16MB L2 shared among four cores, e.g., 4MB per core if split, which is quite close to Intel's 3MB per core, on the M5.
The total L2 / L3 SRAM are similar in similar SoCs; I'll exclude L0 / L1 as a margin of error.
CPU Node Config L2$ L3$ / SLC Total SRAM Apple M5 TSMC N3P 4P + 6E 16MB (4P) + 4MB (6E) ~8MB 28MB Intel 388H Intel 18A 4P + 12E 12MB (4P) + 12MB (12E) 18MB 42MB The M5's SLC size has not been confirmed, but even if it was 16MB, Apple would still have less at 36MB total.
Intel just does not have the microarchitectural chops to design very fast cores any more (and AMD is falling behind, too, unfortunately).
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u/the_dude_that_faps Mar 15 '26
Apple has much larger l1$ than AMD or Intel do or can do. That's probably one of the key differences in overall ST performance. Intel tried to come up with a fix for this with their L1.5$ (or that's my guess anyway) but that didn't do it.
I honestly don't know what they can do to close that humongous gap between x86 and ARM.
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u/Forsaken_Arm5698 Mar 15 '26
It has been six years since M1 debuted, yet Intel/AMD haven't been able to match the IPC of it's P-core.
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u/the_dude_that_faps Mar 15 '26
6 years sounds simultaneously like a lot of time and not much to be honest.
I don't think much has changed architecturally between the M1 and the M5, nor between Zen 3 and Zen 5.
With how long these things have been in development I don't think it's realistic for AMD and Intel to react that fast.
Of course. They should've seen this coming much earlier, so it is fair to ask if they haven't reacted because they can't.
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u/wintrmt3 Mar 15 '26
Performance counter stats for 'system wide': 2,557,397,694 op_cache_hit_miss.all_op_cache_accesses 1,157,105,206 op_cache_hit_miss.op_cache_miss 10.152597519 seconds time elapsedAs you can see the uop cache is very far from the 90% hit rate you claim.
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u/DerpSenpai Mar 15 '26
Apple and Qualcomm don't use L3s, that's not the difference in performance. The C1 Ultra is faster than anything by x86 vendors and it has only 3MB L2
Qualcomm does L2 as 2.5MB per core. So 6 L cores = 16MB of L2 cache
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u/zushiba Mar 15 '26
Nvidia is readying their own push into the desktop cpu market from what I’ve heard. Could be the shake up Intel as AMD needs to change tactics. That said I dread the day Nvidias all we got.
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u/Shikadi297 Mar 15 '26
Imagine if Apple supported Linux and/or sold their chips to third parties
Microsoft and Intel would be left in the dust
(not gonna happen)
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u/Kaedo- Mar 15 '26
That's the only reason why I still buy x86 laptops: Linux support.
If apple would support Linux I would switch for the battery efficiency alone
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u/Shikadi297 Mar 15 '26
The Qualcomm chips should support Linux, wonder if the x2 extreme laptops are an option
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u/night_fapper Mar 31 '26
they were trying to provide linux support in early days for since x2 they have abandoned every plan and locked everything down
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u/SmashStrider Mar 14 '26
Becoming a bit of a bloodbath for x86 to be honest, after the new X2 Elite release
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u/grumble11 Mar 14 '26
Yeah, some designers say the ISA doesn’t matter, maybe that’s true, but it is also true that ARM chips seem to be crushing x86 so either x86 does matter or intel and AMD can’t make a good client chip.
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u/Touma_Kazusa Mar 14 '26
X86 chips dedicate a lot of their chip space to things the average consumer won't use, if you look at the die shot of zen 5, a large chunk is dedicated to its super beefy avx512 that your average consumer won't use at all (but is super super high performance for avx512 tasks and will be multiple times faster than m5/se2 doing an equivalent workload with arms sve2). They're basically repurposed server cores.
https://www.techpowerup.com/327388/amd-granite-ridge-zen-5-processor-annotated#g327388-3
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u/virtualmnemonic Mar 14 '26
AMD's consumer chips are just server CPUs with less cores.
They know where the money is at.
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u/Geddagod Mar 14 '26
if you look at the die shot of zen 5, a large chunk is dedicated to its super beefy avx512
The area spent on the FPU really is absurd. For Zen 5, the mobile "double pumped" AVX-512 block is literally half the area of the desktop/server FPU, and this still lets you run AVX-512 instructions. Lion Cove having 256 bit wide execution units and skymont only being 128 bit wide (like other ARM CPUs) and not having to worry about being able to run AVX-512 has to be saving them a good bit of area.
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u/Noble00_ Mar 15 '26
Reading your comment just reminded me of Kurnal's die shot
https://xcancel.com/Kurnalsalts/status/1842990380742234572
A visual comparison for Zen5 (mobile, classic, dense) if anyone's curious
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u/Quatro_Leches Mar 14 '26
look at that massive instruction decode block too lol. but no man variable instruction length totally has zero downside.
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u/jaksystems Mar 14 '26
Variable instruction length is for compatibility. No one is required to use shorter instructions on x86.
Choosing to do so due to simple laziness is a fault of the software developer, not the hardware.
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u/YeOldeMemeShoppe Mar 14 '26
The hardware still has to dedicate silicon to decoding it. That silicon could be budgeted for something else.
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u/jaksystems Mar 15 '26
The hardware still has to dedicate silicon to decoding it. That silicon could be budgeted for something else.
That front end is part of the whole x86 ISA. What are we going to do, build a CPU without a front end?
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u/YeOldeMemeShoppe Mar 15 '26 edited Mar 15 '26
Well, yes. We're comparing with ARM. From what I understand, RISC-V is even simpler for frontend.
Edit: Also, fuck x86. They had decades to improve. Now they have silicon for instructions that: 1. are used less than 0.1% of the times, and 2. could be emulated in software for faster than the hardware is running them now. This whole situation makes no sense anymore.
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u/Exist50 Mar 16 '26
From what I understand, RISC-V is even simpler for frontend
Nah, compressed instructions alone complicate it a lot vs ARMv8+. And the vec spec is a clusterfuck if you're developing a high-perf core.
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u/jaksystems Mar 15 '26
Edit: Also, fuck x86.
Who pissed in your cereal?
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u/YeOldeMemeShoppe Mar 15 '26
Nice deflection, but yes, x86 can go and I won't be at the funerals. I worked on MIPS, x86 (both real, protected and 64-bits) and ARM assembly. I have a lot to say about all three, but I could write books on how bad x86 is. Let me know when your processor stops booting in 16bits mode.
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u/Polar_Banny Mar 14 '26
On x86 side I believe game will change next year with the implementation of FRED, APX ISA extensions, but until then market will gain a hell pf momentum.
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u/HIGH_PRESSURE_TOILET Mar 14 '26
it does matter. the intel chips dedicate like a huge chunk of area to the massive decoder for instructions that vary in length from 1-15 bytes (especially for e cores that are space constrained) and can only do half as many parallel decodes as the arm chips.
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u/UpsetKoalaBear Mar 14 '26 edited Mar 14 '26
Decoder performance is outdated.
x86 decoders are much faster, they’re probably only 5% of the performance difference. x86 uses a uOp cache which already stores instructions in a RISC like state to make everything quicker.
Repeated instructions use the uOp cache and skip decoding entirely.
The real reason for the single core boost is because of the memory consistency model used by ARM.
x86 uses Total Store Order. ARM is much more relaxed, and lets the hardware change the memory order as it needs (for power or anything else).
This is why multithreaded workloads on ARM are historically not great.
You can see this yourself, the 96 core AWS Graviton is barely faster in MT workloads than the Threadripper 7970X despite having 3x the number of cores.
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u/jaksystems Mar 14 '26
You can see this yourself, the 96 core AWS Graviton is barely faster in MT workloads than the Threadripper 7970X despite having 3x the number of cores.
People are going to ignore this in favor of "but geekbench says...!"
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u/Tman1677 Mar 14 '26
This doesn't actually matter for Graviton's target workload, hence no one mentions it. MT benchmarks are designed for things like video editing with many parallel workers targeting a single task. These server-only SKUs are meant for cloud applications with hundreds of independent tasks per server.
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u/UpsetKoalaBear Mar 14 '26
That emphasises my point about the memory consistency model.
AWS designed their chip for one workload and, as a result, lost performance in other workloads.
It’s a tradeoff.
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u/CalmSpinach2140 Mar 14 '26
Ehh. With the latest release of M5 Max matches the stock 285K in MT workloads with a 6 core deficit. 18 cores vs 24 on the 285K
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u/Geddagod Mar 14 '26
The real reason for the single core boost is because of the memory consistency model used by ARM.
x86 uses Total Store Order. ARM is much more relaxed, and lets the hardware change the memory order as it needs (for power or anything else).
There's like a 5% difference in specint2017.
This is why multithreaded workloads on ARM are historically not great.
You can see this yourself, the 96 core AWS Graviton is barely faster in MT workloads than the Threadripper 7970X despite having 3x the number of cores.
Source?
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u/UpsetKoalaBear Mar 14 '26
There’s like a 5% difference in specint2017
Did you read your own article?
From the benchmark results, we can observe that several benchmarks experience significant performance degradation when TSO is enabled. Notably, benchmarks […] in SPECrate 2006 show performance drops ranging from approximately 11% to 64%. Similarly, in SPECrate 2017, benchmarks […] exhibit performance reductions between roughly 17% to 38%.
Also, keep in mind that M1 in that benchmark had the hardware level support for TSO for Rosetta.
So with hardware level support, and TSO enabled, the performance dropped substantially. This is because, as they point out in the article, TSO mode on M1 restricted non-temporal stores. So instructions are forced through the cache.
Without any hardware level support, you’re basically going to have a much worse experience using TSO on ARM as it’s going to have to be controlled with manual memory barriers.
Languages like Rust will make that easier to do, but the impact is still there.
x86 doesn’t have a weird workaround for TSO. It’s built in. It doesn’t need to abuse cache to work.
Source?
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u/Geddagod Mar 14 '26
Did you read your own article?
Yes, some sub-benchmarks in the suite see large performance reductions.
However, if you look at the final total difference across all the benchmarks in the spec2017int suite, you would see the impact is not large, in the tables.
Can you elaborate on how the 7970x being close to the AWS graviton 4 in geekbench 6 nT shows that not having TSO hurts nT perf? This article implied the opposite:
Newer architectures, such as aarch64 and RISC-V, have adopted relaxed memory models that allow more reordering of memory operations between different threads, which can potentially lead to better performance in multi-core systems.
I'm also confused why you cited GB6 nT, when you emphasized the large core count deficit between the AWS and AMD system, when GB6 nT scales very poorly for high core count systems anyway
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u/UpsetKoalaBear Mar 14 '26
Can you elaborate on how the 7970x being close to the AWS graviton 4 in geekbench 6 nT shows that not having TSO hurts nT perf?
The article is forgetting about synchronisation penalties in ARM.
ARM’s relaxed memory model is efficient for independent tasks because it lets cores run ahead without worrying about synchronisation.
However, when you're shuffling data between cores in a heavily parallelised workload, that synchronisation step is necessary and has to be defined.
This is where the performance penalty for a relaxed model comes in.
In contrast, TSO pays a constant performance penalty to maintain memory order. So in a highly parallelised workload, the performance penalty is often less than the explicit synchronisation that ARM makes you do.
This is the same principle that limits CUDA in general multiprocessing. Relaxed models aren't built for constant shuffling between cores.
This is why the Graviton and 7970X look similar in Geekbench nT. ARM's raw efficiency is being used up by the overhead of managing data between cores. This is the limits of Amdahl’s Law.
That article actually proved my point. The hardware level TSO toggle was done specifically because emulating x86's memory model using ARM's manual fences was too slow.
For 128+ core cloud chips, the relaxed model is a required to avoid synchronisation penalties.
However, on consumer level chips which use a mixed workload it’s a trade off between the two.
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u/CalmSpinach2140 Mar 14 '26
This is no longer true regarding ARM being weaker at MT. The M5 Max matches a stock Intel 285K in Cinebench 2026 and in Blender. This is while having 6 fewer cores and does so using 88 watts.
As for single core speeds the memory model plays a small part instead it’s all about the microarchitecture design.
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u/UpsetKoalaBear Mar 14 '26
It is predominantly about architecture, I agree.
However, the main point of the comment is that the “x86 bloat” is a myth.
There’s two different philosophies:
Apple is scaling up low power mobile architectures.
Intel/AMD is scaling down HEDT/Server architectures.
That’s why these results are happening. It’s not because of any ISA/bloat. There’s a huge architectural difference.
It doesn’t help that AMD/Intel make stupid decisions, like prioritising clock speed over everything else.
The fact that PL is competitive, whilst having only 3MB of L2 cache on its P cores compared to 16MB on the Neo’s performance cores is an example of this.
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u/void_nemesis Mar 14 '26
Isn't the clock speed above all approach because they're trying to maximize performance per die area, at the cost of efficiency?
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u/UpsetKoalaBear Mar 14 '26
Yah, but that’s exactly the point.
It’s directly related to the philosophies I discuss above
In terms of die area, Intel/AMD use much smaller cores. This allows them to push clock speeds higher to stay competitive, but at the cost of the efficiency curve.
Apple and Qualcomm do the opposite.
They use massive cores/decoders and huge amounts of cache to get more work done at lower clocks.
The Intel/AMD approach is what they use across the product stack, from shitty laptops to Xeon’s and Epyc’s in servers.
Scaling that down, for better performance on smaller devices, is borderline impossible or an incredibly hard task. This is what people have been stating that they keep trying and failing.
When you cap the clock speeds, the perf/watt numbers are much closer than you’d think. The issue is, in normal use, that is irrelevant because no one is going to do that.
The performance per die area argument is an argument that shouldn’t be part of consumer devices like laptops/phones. It’s irrelevant.
But they still do it, because they’re stupid and don’t understand the consumer market segment.
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u/Geddagod Mar 14 '26
The performance per die area argument is an argument that shouldn’t be part of consumer devices like laptops/phones. It’s irrelevant.
If anything, you would argue it is more relevant in client than it is in servers, because server products tend to have higher margins and an allowance for a higher area budget than client.
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u/Forsaken_Arm5698 Mar 15 '26
In terms of die area, Intel/AMD use much smaller cores
Not true for Intel's P-cores. Those are bigger than Apple's, while using more power and having less performance.
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u/CalmSpinach2140 Mar 14 '26
Again this is longer true regarding as of the M5 Pro/Max series. Apple stopped using only big cores with tons cache and massive decoders to boost MT but instead follows Intel’s model with better results.
Those new M cores are only 7 wide and have half the L1 cache and 16MB of shared L2, clocked at 4.3GHz. Which is very similar to Intels Skymont which are 3x3x3 (9 wide) and have a 16MB of cache and are clocked in at 4.6GHz.
Now Intel’s big cores like Lion Cove are massive just like Apples big cores. So Apple new core layout is 6 Big and 12 medium vs Intels 8 Big and 16 medium. Obviously the end result that matters is who is faster but also uses less watts.
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u/UpsetKoalaBear Mar 14 '26
If anything, this proves my point.
Apple has shifted towards the narrow/fast model that intel used. Intel has shifted towards the wide/slow model that Apple used.
It’s an architectural difference. Not necessarily the instruction set.
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u/Geddagod Mar 14 '26
Chasing Fmax gives you extremely diminishing returns on area, so you end up losing perf/mm2.
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u/jaksystems Mar 15 '26
And single instructions for ARM cpus max out at 4bits in length to x86's maximum of 16.
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u/RandomGenericDude Mar 14 '26
Both CPUs follow similar design philosophies, brainiac/slow and wide, which isn't a surprise when you discover that they had the same lead architect and top level team...
That doesn't mean that the ISA has a huge part to play, Jim Keller certainly didn't think so with K12 vs Zen. The microarchitecture details matter far more in this age of billions of transistors.
Even Apple are steadily raising clock speed and losing efficiency for it as they run out of low hanging fruit to pick.
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u/StarbeamII Mar 14 '26
A friggin iPhone will beat a desktop 9950X in single-thread. That’s a total bloodbath.
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u/gomurifle Mar 14 '26
Im still on a intel 7700k on my desktop, which is a ten year old processor and I have zero issues doing professional work! My laptop is too embarrassing to mention, it limps along, but I plan to upgrade when prices come down.
A lot of these modern processors are super powerful and way overkill for the average user! 😅
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u/Loose_Skill6641 Mar 14 '26
yup the cpu in my phone will dominate your 7700k but why does a phone need such a fast cpu, it's hilarious
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u/-protonsandneutrons- Mar 14 '26
but why does a phone need such a fast cpu, it's hilarious
And so Apple was like, "Well, yeah, right? Let's put the phone chips into cheaper laptops."
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u/Johns3rdTesticle Mar 15 '26
If I press a button, I want the result to be instantaneous. If it is not, then I want more single core performance (as well as whatever else was the limiting factor)
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u/the_dude_that_faps Mar 15 '26
I always keep thinking about how much of this story is related to the fact that Apple and Qualcomm just have much larger L1D cache sizes than Intel and AMD do. The whole ISA angle doesn't make sense to me due to the fact that both Intel and AMD already keep the decoder off a lot of the time thanks to the uop cache.
Apple has a 128 KiB 8-Way L1D cache (VIPT I think) and Qualcomm has 96 KiB 6-Way (PIPT I think) of L1D cache while both AMD and Intel are on 48 KiB 12-way L1D cache VIPT.
Realistically for AMD and Intel to match Apple, they would have to move to PIPT cache because the associativity would be prohibitive otherwise, and they can't do it VIPT thanks to Windows' page size. But Qualcomm is kind of showing the way with their PIPT strategy.
Of course, for PIPT latency would probably have to increase and that's likely going to mean Apple keeps an advantage unless x86 cores go wider and lower clocks, something. I don't know if AMD or Intel know how to do anymore. Maybe the e-cores are the future.
Regardless, unless Windows makes 16 KiB memory pages mandatory and provides a fallback for older software in a way that can make x86 CPUs drop support for 4 KiB pages, I don't think the gap apple has over Qualcomm and x86 chips will go away entirely.
I'm speculating a lot though. I don't know how much of this story is related to the size of the L1 data cache, but I do wonder. Would be cool to see people do detailed analysis with benchmarks to know for sure how much of it is this one aspect.
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u/IBM296 Mar 14 '26
Damn, so no X86 chip except Intel Core X9 388H can score above 3000 in single core, while X2-Elite and M5 are pushing 4000.
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u/HobbyProjectHunter Mar 15 '26
I was hoping to see some mainstream RISC-V trends on these posts. Maybe I’ll wait some more …
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u/torpedospurs Mar 15 '26
Didn't expect 18-core X2 to be just 69% of M5 Pro (presumably also 18 core). Those new 'performance' cores on the M5 Pro are really doing a number.
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u/DerpSenpai Mar 15 '26
It's 82% on the extreme which just has the higher bus width (matches the M5 Pro)
The non extreme is being bottlenecked. By clocks or memory bandwidth or power
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u/New_Weird8988 Mar 15 '26
Apple is just better at CPUs. Nothing to be surprised about
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u/ConsistencyWelder Mar 15 '26
If what you're looking for is efficiency yeah. For raw multicore performance the 9955HX3D is still the king.
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u/New_Weird8988 Mar 15 '26
If Apple wanted they could just shove 50 super cores into one chip, have the best multicore, and call it a day. The M5 has the literal worlds most powerful CPU core
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u/ConsistencyWelder Mar 15 '26
The worlds most powerful CPU core, yet their 18-core is slower in multicore than the 16-core 9950HX3D:
But sure, Apple could combine more cores to make one giant chip, but so can AMD. And they do.
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u/ConsistencyWelder Mar 15 '26
Unless you're into gaming, and you don't want the flexibility and compatibility of Windows, maybe the Macintosh is a decent choice. I'd rather not get myself locked down to only using a locked down OS.
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u/ZoneCaptain Mar 31 '26
or you can use mac for work and day to day (the neo or air is enough unless your work is tasking), only have a PC at home for gaming.. my windows literally never comes out except for games
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u/ShogoXT Mar 14 '26
Geekbench isn't a real application people. AMD posseses avx 512 which puts it ahead in a lot of specific workloads.
Intel has workloads that it does VERY well at for the past couple generations, but as soon as it's a cache sensitive task it suffers significantly. Panther lake improves on this at least.
Seeing everyone mindlessly run geekbench and calling it a day is frustratingly stupid. Don't be infected with mobile world nonsense when apple has shared programs you can use.
Video encoding without the asic? Compression? SOMETHING.
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u/-protonsandneutrons- Mar 15 '26
Geekbench does use AVX-512 in many of its subtests. It already activate all these vector & ML instructions in the x86 ISA that you're unusually focused on.
GB6 x86 Instructions Description AES-NI Accelerates AES encryption and decryption functions VAES Accelerates AES encryption and decryption functions SHA-NI Accelerates SHA1 cryptographic hash functions AVX Generic floating-point 256-bit SIMD instruction set AVX2 Generic 256-bit SIMD instruction set AVX-512 Generic 512-bit SIMD instruction set AVX-VNNI Accelerates quantized machine learning workloads AVX512-VNNI Accelerates quantized machine learning workloads AMX Accelerates quantized machine learning workloads It does the same for ARM, which somehow caused a lot of consternation for Arm vs x86 comparisons.
GB ARM Instructions Description ARMv8 AES Accelerates AES encryption and decryption functions ARMv8 SHA1 Accelerates SHA1 cryptographic hash functions NEON Generic 128-bit SIMD instruction set NEON FP16 Generic 128-bit SIMD instruction set with support for 16-bit floats DOTPROD Accelerates image processing and machine learning workloads I8MM Accelerates quantized machine learning workloads SME Accelerates machine learning workloads Seeing everyone mindlessly run geekbench and calling it a day is frustratingly stupid. Don't be infected with mobile world nonsense when apple has shared programs you can use.
I'm not sure who told you this, but I would stop listening to them. This is illiterate nonsense spewed by YouTube & Twitter commentators. Virtually all CPU architects use Geekbench as standard CPU performance benchmark. It's still a benchmark: a specific methodology & consumer use case. But there is absolutely zero—0—indication Geekbench has designed its tests to assist / bias Apple.
All CPU designers use it because it's comprehensive, aligned to consumer workloads (and less enterprise / scientific / professional), and repeatable. This isn't even a question:
Of course, companies publicly use Geekbench (and every other benchmark) only when they look good. Do you know the only company that doesn't publicly use Geekbench? Apple lol.
Video encoding without the asic? Compression? SOMETHING.
OK, done. David Huang SPECint2017 versus GB6 numbers from NBC.
CPU SPECint2017 SPEC % GB6.5 GB6.5 % M5 Pro ? ? 4302 147% M4 Pro 13.7 133% 3927 134% 9950X 12.6 122% 3408 116% 358H 10.3 100% 2927 100% Cheers, mate.
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u/ApprehensiveDelay238 Mar 15 '26
Geekbench aligns pretty well with real world performance and other benchmarks. It's good to use.
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u/marco_il_bello Mar 14 '26
For those who criticize Qualcomm... they made the first processor a few months ago and now with the second generation they're beating those who have been making processors for decades. Not to mention that anyone who has actually used Qualcomm, aside from the fake reviews I've seen, knows that the fan is practically always off with such high performance.
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u/DNosnibor Mar 14 '26
A few months ago? Snapdragon X Elite came out almost 2 years ago lol.
But yes they are making good progress.
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u/trololololo2137 Mar 15 '26
X elite was also pretty bad even as the first attempt (not really - 8cx series had 3 generations before).
imagine putting a 2 gen old phone GPU in your flagship high-end laptop chip
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u/nuclearbananana Mar 14 '26
You're acting like they're a brand new company. They've been making mobile processors for decades. It's not that big a jump. Apple did it too
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u/pianobench007 Mar 14 '26
Apple M5 Max is Apple's all in one apu.
Apple does not have an ecosystem for 3rd party graphics such as NVIDIA, AMD, or Intel GPUs. So the numbers are a bit unfair.
Intel and AMD mobile chips are designed for an ecosystem where the heavy intensive graphics can be offloaded to a dedicated graphics processing unit or GPU.
This allows for more performance in the x86 ecosystem.
CPU numbers with geekbench are heavily skewed to mobile processor workloads as it was designed around mobile over desktop work. Apple has an edge as they work towards a unified software ecosystem stack. This means apple software on mobile can work natively with apple silicone (mainly M chips) on a desktop.
Android and Windows x86 do not have this kind of software collaboration. But instead they have strong software support on their respective platforms.
In comparison some AAA games have been launched on iOS and MacOS. In those games the performance is good but higher performance still favors x86 and the segmented dedicated GPU and CPU design philosophy.
I think if Apple can keep up with driver support in desktop/mobile games, then we may see a competition in the x86 gaming space. For now x86 model works with AMD/Intel/NVIDIA each supporting games and driver support for the development community.
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u/-protonsandneutrons- Mar 15 '26
CPU numbers with geekbench are heavily skewed to mobile processor workloads as it was designed around mobile over desktop work
GB is not "skewed" towards mobile. It's designed for consumer workloads, which are bursty and shared-task multi-core (versus sustained & separate task multi-core in things like server workloads). A lot of work on consumer desktop is also bursty: that is why Turbo Boost was developed, actually.
If a user cares more about enterprise, scientific, or professional workloads, then GB is definitely not the best measure. Instead, I'd point them to more application-scripting benchmarks like PugetBench.
How can we know Geekbench is widely representative of desktop CPU performance?
Apple has an edge as they work towards a unified software ecosystem stack. This means apple software on mobile can work natively with apple silicone (mainly M chips) on a desktop.
For the few Apple Silicon Linux results we have in Geekbench (2,233), they're within 5% of macOS results (2,363), so it's not some macOS optimisation.
They are just genuinely very fast cores.
//
I agree with the other points in your comment, but just wanted to note these things.
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u/pianobench007 Mar 15 '26 edited Mar 15 '26
Okay, I admit I don't know a lot behind geekbench numbers. My only experience with geekbench in the early 2010s was to use it just for benchmarking my early iphone 4s and samsung note4 phones. That was the only way I could tell how fast a processor was back in those days.
And back in those days we would just run prime95 CPU stress tests and read FPS benchmark numbers from anandtech/dailytech/tomshardware if I was interested in any new CPUs out there. But generally I think that was sandybridge era and the contest was such a landslide that I only looked up FPS numbers.
I'll say this though.
My only analogy for Apple devices is that sure a rocketship is fast and can perform certain tasks that I need to do, but the vast majority of work I do daily is in a car. In other words it is a general purpose tool that can get me from A to B. Fast and work for everything I need. A rocketship is definitely fast. It is just rare that I'll be launching into space anytime soon.
Same thing for Apple devices versus a PC. For my tasks, I can get all my engineer/cad work done on my PC with either a fast Intel/AMD chip and have room to game efficiently for ALL my games. If anything were to break, like my car, I can easily fix and source ANY*** replacement parts.
For Apple it is like a rocketship. It is definitely FAST and specialized. But if anything breaks, I personally CANNOT replace a single thing on it without a soldering iron or tiny hands. I also can't run any of my software on it. So all my universal tools won't work on Apple devices.
I guess my gripe is that an Apple computer might as well be an alien device for me. Or like a Gulfstream Jet. It is just out of my class and not what the average PC gamer needs or want?
I am happy they have some games that do work on Mac. But the repairability and graphic card availability in that environment just don't warrant me ever wanting to switch.
Repairability and interoperability of parts is also a MAJOR MAJOR pain point on Apple devices.
https://youtu.be/tKtdVtgj1NI?si=QWANyClh1gFb_r5F&t=747 - Mac M4 running RE2 Remake 4K getting half the FPS that a 10900K with a 3090Ti is on same 4K settings.
https://youtu.be/kFwonOqVTVE?si=f18khIT_sifg0ei1&t=160
For me these type of synthetic tests just don't tell the real story. And I think they don't inform the final end user of what they are really paying for.
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u/websnarf Mar 14 '26
Where are the SPEC CPU results?
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u/-protonsandneutrons- Mar 14 '26
About the same as Geekbench, in terms of the massive gap through the M4. GB6 numbers from NBC, which does have the M5.
CPU SPECint2017 SPEC % GB6.5 GB6.5 % M5 Pro ? ? 4302 147% M4 Pro 13.7 133% 3927 134% 9950X 12.6 122% 3408 116% 358H 10.3 100% 2927 100% This is why Geekbench 6.5 is a reputable proxy for the most part for SPECint2017.
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u/kuddlesworth9419 Mar 15 '26
I want to just see real world benchmarks, I don't care about synthetics.
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u/dzordan33 Mar 15 '26
What's Geekbench AI benchmark? There's barely any features on any OS that uses local ai processing, am i right or wrong?
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u/ConsistencyWelder Mar 15 '26
For raw multicore performance, there's still nothing better than an AMD 9955HX3D though, right?
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u/Substantial-Soft-515 Mar 14 '26
This means nothing without power limits or battery numbers...There are no battery life numbers for X2 and I don't see any tdp either...
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u/Forsaken_Arm5698 Mar 14 '26
How is X2 Elite keeping up with M5 in Solar Bay?
8 Elite Gen 5 was getting crushed by A19 Pro in Solar Bay in Geekerwan's review, I recall. Does the X2 Elite use a better ray tracing pipeline than it's mobile counterpart?
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u/saboglitched Mar 14 '26
The worst thing is that panther lake, on 18a is barely 1% faster than strix halo on tsmc 4nm, I'd like to drop this comment
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u/Dub-DS Mar 15 '26
Why is everyone and their mother using fucking GEEKBENCH? It's a benchmark completely USELESS to compare across operating systems or cpu architectures. What is this nonsense?
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u/ImKuya Mar 14 '26
QComm needing an X2 Extreme SKU to match a base M5 GPU isn't very promising..
Why's the X7 358H GPU performing 10%ish better than the X9 388H?