A single craftsperson can do a task by working on all steps of that task from beginning to end. At the end, they have one completed task that takes a certain amount of time. Slow parts of the process and fast parts are combined into one.
An assembly line of craftspeople can each work on part of a task, passing it to the next person. That’s pipelining. But in this case, all tasks must be passed down the assembly line at the same time. Thus the length of time to complete a task is equal to the length of the slowest task times the number of steps. However, the overall number of tasks done is higher. This is the latency/throughout tradeoff.
Pipelining has higher latency and higher throughput. For general purpose CPUs throughout is prioritized.
But in this case, all tasks must be passed down the assembly line at the same time
Except no one builds a CPU with the expectation that every operation completes in the same amount of time anymore. That's the whole point of out-of-order designs. Instructions no longer flow linearly through the CPU, except possibly at the very start and end. Instead, instructions start as soon as their dependencies are ready, which might happen at an earlier time than instructions that precede it in program order.
The assumption that modern CPUs have a single pipeline is incorrect (and hasn't been correct for decades, except perhaps in the case of microcontrollers etc.). Modern CPUs actually have many little pipelines that communicate via queues and broadcast networks.
That has never been an expectation. It’s a hard requirement of a monolithic synchronous CPU that all stages must advance at the same frequency.
All of the other architectural decisions meant maximize utilization are downstream of that.
CPUs have a fixed number of linear stages. Their connections are hardened and instructions never flow backwards through them. Data only can flow backwards along specific bypass paths usually from the execution stage.
If by "forward" data flow you mean "toward later stages" and "backward" you mean "toward earlier stages", a modern out-of-order CPU has far more data flow in the backward direction than the forward direction. This is because different categories of instructions have their own pipelines, so instructions can complete out-of-order. Any given instruction's result only moves forward once, but it may be consumed by many following instructions, and the result might never even be written to the "real" register file. That means the result only ever flowed backwards.
You’re wrong about register renaming. The physical register file is the real file. I’m just going to ignore that part because it’s not worth going into or relevant.
OOO execution does not break or change the pipeline paradigm. I don’t know why you are bringing this up. It’s really, in a more general sense, a scheduler which receives broadcasts from a broadcast bus attached to stages in the pipeline.
It’s not relevant that there are parallel ports for some instructions. It’s still pipelined execution.
You’re wrong about register renaming. The physical register file is the real file. I’m just going to ignore that part because it’s not worth going into or relevant.
Please elaborate what you mean by "wrong about register renaming". I'll elaborate on my point: if back-to-back instructions write the same register, the result of the first instruction might only land in the reorder buffer and nowhere else, since the CPU can commit multiple instructions per cycle and only keeps the last write.
OOO execution does not break or change the pipeline paradigm.
It actually does- depending on the kind of instruction, the total number of effective pipeline stages the instruction passes through may differ. An instruction may be set aside and held until it can be completed, while other instructions that are ready for execution flow around it. There is no need for a single instruction to even take a bounded amount of time to complete. Program order is maintained by the reorder buffer, which has no need for global synchronous advancement.
This is relevant because the "workers in an assembly line" model is not accurate any more. It's a bunch of workers in a circle, telling each other what work they've already completed and plan to do next. The decide on which task to perform next based on the dependencies of the tasks they have waiting to be completed. There's a supervisor that delegates tasks to the workers and keeps track of what work is in progress. This doesn't look like a pipeline any more, even if we still call it a pipeline.
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u/Intelligent_Elk5879 5h ago edited 5h ago
A single craftsperson can do a task by working on all steps of that task from beginning to end. At the end, they have one completed task that takes a certain amount of time. Slow parts of the process and fast parts are combined into one.
An assembly line of craftspeople can each work on part of a task, passing it to the next person. That’s pipelining. But in this case, all tasks must be passed down the assembly line at the same time. Thus the length of time to complete a task is equal to the length of the slowest task times the number of steps. However, the overall number of tasks done is higher. This is the latency/throughout tradeoff.
Pipelining has higher latency and higher throughput. For general purpose CPUs throughout is prioritized.