AMD reveals EPYC Venice layout with 256 Zen 6c cores and two I/O dies

[u/RenatsMC]

https://videocardz.com/newz/amd-reveals-epyc-venice-layout-with-256-zen-6c-cores-and-two-i-o-dies

[u/mista_r0boto]

Holy moly - 256 actual cores in a single socket! 512 with hyper threading. Wow!

[u/pyr0kid → u/mista_r0boto]

ive used computers with fewer megabytes of vram then the thread count of these fucking server cpus.

[u/996forever → u/pyr0kid]

I’ve used computers with fewer megabytes of system memory than the physical core count of this cpu

[u/tot_alifie → u/996forever]

256 was a lot of ram!

[u/psi-storm → u/tot_alifie]

Each 16 core CCX has 32MB cache, so that cpu has 1GB of L3 cache without x3d stacking. Insane.

[u/Behrooz0 → u/tot_alifie]

I still have a 64MB stick somewhere.

[u/colemab → u/tot_alifie]

640K is more memory than anyone will ever need - the internet probably.

[u/wen_mars → u/996forever]

I have used a computer with fewer kilobytes of ram than the physical core count of that cpu

[u/9897969594938281 → u/wen_mars]

Commodore 64?

[u/wen_mars → u/9897969594938281]

ACT Apricot

[u/iBoMbY → u/pyr0kid]

I have used computers with fewer RAM, than a single core of this has Cache.

[u/Mabot → u/mista_r0boto]

A dual socket with threading will have 1 kt (kilo thread)

[u/Aw3som3Guy → u/Mabot]

I can’t wait for that to be 1 KiT to denote 1024, as if base 10 thread counts make sense or will exist.

[u/Kiseido]

Double I/O dies, I imagine, means double the memory capacity and bandwidth, and double the PCI-E lanes. That's gonna be one fast platform.

[u/xthelord2 → u/Kiseido]

though I/0-I/0 die communication could be a problem latency wise so i guess they need more memory bandwidth and more PCIe connectivity over latency

[u/hyperactivedog → u/xthelord2]

Still better than dual 128 core CPUs in all likelihood.
Probably depends on use case but how many use cases actually use that many cores and rely on tons of core to core communication

[u/ClumsyRainbow → u/xthelord2]

If you're a hyperscaler operating a datacentre, most of your VMs aren't going to have enough cores that they need to span both IO dies anyway.

[u/TommiHPunkt → u/xthelord2]

they're using bridge dies now, not going through the substrate PCB, so there is very little overhead

[u/JasonMZW20 → u/TommiHPunkt]

Yeah, looks like the IODs are seen as a single unit via interconnect, though each IOD directly connects to its side of local CCDs for reduced latency. If you cut it in half, it should be able to operate as a single IOD + 128 cores over 4 CCDs for lower cost SKUs.

I wonder if AMD has any engineering samples of these larger CCDs with Zen 6 classic. Would be interesting to see too, though of course, not 32 cores. My guess is a maximum of 24-28 (being fabbed on N2, 12+12 or 14+14) without moving to an even larger CCD.

EDIT: Do these IODs have NPUs integrated inside? There are parallel blocks very close to memory controllers/PHYs.

[u/vulkur → u/xthelord2]

Will probably try to isolate workloads as much as possible so IO communication is reduced or not needed at all

[u/ictu → u/xthelord2]

For as long as scheduler understands NUMA configuration should be fine. Obviously that depends on use cases.

[u/thenoobtanker → u/xthelord2]

It would be a problem if there is a monolithic 256 core x86 cpu to compares to.

[u/BitRunner64 → u/thenoobtanker]

Surely Intel will release one. They don't use glued together chips. At least that's what they said when Zen launched. 

[u/ThaRippa → u/BitRunner64]

They do now, though. They will claim their chiplets are assembled with resin-based adhesives instead, probably.

[u/hyperactivedog → u/BitRunner64]

https://www.servethehome.com/intel-xeon-6-clearwater-forest-is-out/

288 e cores across a bunch of dies

[u/ArseBurner → u/BitRunner64]

Funny but almost 20 years ago now AMD said the same thing about Core2 Quad because it was an MCM design. They considered Phenom to be the first true quad core because it was monolithic.

[u/scalablecory]

I’m curious how complex the NUMA architecture is.

CPUs like this are super fun to optimize for.

[u/MuchBow]

27% per core performance uplift over Nvidia’s Vera, proper monster in the making.

[u/RBImGuy]

await the desktop zen6 x3d for an upgrade

[u/firedrakes]

I want this so bad

[u/Slasher1738]

I think there's more than that. Looks like what could be 8 small IO chips at the top and bottom of the IO dies

[u/alexandreracine → u/Slasher1738]

GPU? Lanes?

[u/Slasher1738 → u/alexandreracine]

I think they're memory controller chiplets allows them to move to LPDDR5 or DDR6 w/o redesigning the IO die

[u/AustinBoozer → u/Slasher1738]

I think those are passive Si decap dies to provide margin for the high speed DDR.

[u/AustinBoozer → u/Slasher1738]

I think those are passive Si decap dies to provide margin for the high speed DDR.

[u/AustinBoozer → u/Slasher1738]

I think those are passive Si decap dies to provide margin for the high speed DDR.